1. Field of the Invention
This invention relates to channel selecting apparatus to be used for such electronic instruments as color television receivers, and, more particularly, to a channel selecting apparatus for quickly tuning broadcast signals that are not transmitted at the regular frequency.
2. Description of the Related Arts
Generally, a channel selecting apparatus in within in electronic instrument such as a color television receiver, an electronic tuner using a variable capacitance diode is used to select the broadcasting station.
The channel selecting apparatus formed using such electronic tuner is, for example, of a voltage synthesizer system or a PLL (abbreviation of a Phase Lock Loop) synthesizer system.
In the channel selecting apparatus of the PLL synthesizer system, generally, the local oscillated frequency is divided by a prescaler, the output of the prescaler is further divided by the divided frequency data from the CPU and is compared with the reference frequency in phase to generate error output voltage. The electronic tuner is driven by the error output voltage to select a channel and there is a large advantage that no presetting is required, as compared with the channel selecting apparatus of the voltage synthesizer system.
The conventional channel selecting apparatus using such a PLL synthesizer is shown in FIG. 12.
FIG. 12 is a block diagram showing an example of the conventional channel selecting apparatus.
As shown in FIG. 12, the television signal received by an antenna 1 is fed to an RF amplifier, is amplified by the RF amplifier 2 and is output to a mixer 4. The mixer 4 mixes the oscillated frequency output by a separately provided oscillated frequency variable oscillator (called a Voltage Controlled Oscillator abbreviated as a VCO hereinafter) 3. Mixer 4 produces a beat signal as of a frequency equal to the difference between the original two frequencies and feeds that beat signal to an IF amplifier 5. The beat signal is amplified in the IF amplifier 5 and is output to an IF circuit 8.
That is to say, the received television signal is amplified by the RF amplifier 2, is then heterodyned in the mixer 4 with a signal from the VCO 3, and is output. A tuner 6 of a so called superheterodyne system is formed of the RF amplifier 2, VCO 3, mixer 4 and IF amplifier 5.
The role of the tuner 6 is, in short, to select a specific signal from the group of many electric waves output from the antenna 1, to control the oscillated frequency of the VCO 3 to output the specific signal as an IF signal 7, and to adjust the frequency of the beat signal obtained in the mixer 4.
For example, suppose that fIF represents an intermediate frequency, fVCO represents an oscillated frequency and fRF represents an input signal frequency, the relations of the frequencies of the input signal and output signal in this step will be as follows: EQU fIF=fVCO-fRF (1)
The output of the tuner 6 is led to the IF circuit 8 to be processed. The out is amplified by the IF amplifier 9 forming the IF circuit 8, is then demodulated as a base band video signal by a video signal detector 10 and is output from an output terminal 30 to a video amplifying step (not illustrated).
Here, an AFT signal detector 11 connected to the output terminal of the IF amplifier 9 outputs a signal (AFT signal) for judging the frequency of the IF signal input into the IF circuit 8, though no circuit form is described, as compared with the regular frequency. That is to say, the AFT signal detector 22 judges whether the frequency is higher or lower than the regular frequency. Therefore, in the receiver, when this AFT signal is detected by an AFT signal detecting circuit 22, the state of the present received signal frequency will be able to be recognized. This AFT signal is fed to a microprocessor 21.
On the other hand, a prescaler 12 forming a part of the PLL circuit is connected to the VC0 of the tuner 6. The PLL circuit 20 is provided to determine the oscillated frequency of the VCO 3. It operates so that the signal of the VCO 3 may be detected and divided in frequency by the prescaler 12. The signal divided in the frequency by a variable frequency divider 13 and the signal which the output from a high precision fixed oscillator 14 is divided by a fixed frequency, divider 15 in the frequency are compared in the phase with each other, and the result of the phase comparison is used to obtain a controlling voltage 17 of the VCO 3 using a loop filter 18. Thus, the oscillated frequency of the VCO 3 can be varied.
A data latch 19 is to take in the divided frequency ratio of the variable frequency divider 13 from a microprocessor 21.
Thus, a PLL circuit 20 is formed as one circuit block of the prescaler 12, variable frequency divider 13, fixed oscillator 14, fixed frequency divider 15, phase comparator 16, controlling voltage 17, loop filter 18 and data latch 19. The oscillated frequency of the VCO 3 is controlled by using this PLL circuit 20.
Here, for example, in case the divided frequency ratio of the prescaler 12 is 1/8, the divided frequency ratio of the variable frequency divider 13 is N, the output frequency of the fixed frequency divider 15 is 7.8125 KHz, when the PLL circuit 20 is locked, the oscillated frequency (fVCO) of the VCO 3 will be represented by: EQU fVCO=N.times.7.8125.times.8=N.times.62.5 (KHz) (2)
The operation when a desired channel is received in the circuit described above shall be explained in the following. Here, the television broadcast channels in Japan shall be explained for example.
First of all, when a broadcast is received by selecting the channel with the microprocessor 21 as a desired channel (for example, the channel 1 from among the plurality of broadcast channels, as the receiving frequency (fRF) of this channel 1 is 91.25 MHz), and the broadcast is tuned with this receiving frequency, as the intermediate frequency (fIF) is 58.75 MHz, by the formula (1), EQU fVCO=fIF+fRF=150 (MHz)
and therefore from the formula (2), EQU N=150000/62.5=2400 (3),
That is to say, if these divided frequency data N are operated on using the microprocessor 21, are fed to a data latch 19, and are set, the oscillated frequency of the VCO 3 will be varied. That is, the frequency of VCO 3 will be able to be tuned to the receiving frequency (fRF) of the channel 1.
Therefore, in the channel selecting apparatus of such circuit formation, when the broadcast signal is not, for example, of the regular fRE frequency but is optionally offset, when the broadcast frequency fSIG of this optionally offset signal 91.5 MHz and mentioned above, from the now tuned channel 1 broadcast the broadcast frequency of 91.5 MHz of the fSIG is tuned, the broadcast will be received on the basis of the data (N=2400) of the formula (3), the output of the AFT signal detector 11 will be led to the microprocessor 21 through the detecting circuit 22. The output will then be detected to see whether it is higher or lower as compared with the present frequency. That is, the frequency regulated by the frequency (91.25 MHz) of the channel 1 will be determined to be the frequency naturally lower then the present broadcast frequency fSIG being received, the divided frequency data (N) will be increased, the frequency will be received again, and the frequency will be received repeatedly several times to achieve the desired frequency. That is, the broadcast frequency fSIG will be received.
The following pertains to a situation where the broadcast signal is to be changed to the broadcast frequency of the channel 2, for example, from the broadcast frequency of the channel 1. When the broadcast signal of channel 2 is not a predetermined fixed frequency (f0) but is optionally offset, for example, when the broadcast frequency of this optionally offset signal is fSIG and both signal frequencies are, EQU f0=97.25 MHz and fSIG=97.5 MHz.
Here, the receiver will not recognize the signal frequency=fSIG. Therefore, the frequency dividing ratio will be changed to receive the regular frequency=f0 of the channel 2 which will be set in the data latch. When the locked frequency of the PLL circuit 20 varies and the tuner 6 tunes a signal with the regular frequency f0 based on the variations, the present signal frequency is tuned with the low frequency and output from the AFT signal detector 11. This recognizing signal is detected by the microprocessor 21, the frequency dividing ratio is gradually increased at any time intervals, the locked frequency of the PLL circuit 20 is varied, then a signal reporting that the tuner 6 tunes with the broadcast signal in the normal state is output from the output of the AFT signal detector 11. This signal is detected by the microprocessor 21 and the variation of the frequency dividing ratio is stopped so that the offset broadcast frequency (fSIG) may be normally received.
However, in such conventional channel selecting apparatus, there are problems. For example, when the regular frequency f0 is made, the broadcast frequency of the channel 2 from the broadcast frequency of the channel 1 and the broadcast frequency fSIG desired to receive greatly vary from this broadcast frequency of f0, as shown, for example, in FIG. 13. The time for receiving the regular frequency f0 of the channel 2 from the state that the broadcast frequency of the channel 1 is being received will be t0-t1 and, in order to receive the desired frequency of fSIG from the frequency f0 of this channel 2, several correcting times are required as illustrated, such long time as the time t1-t3 will be required. Regarding the channel selecting apparatus using such system, these problems are not solved.
As in the above, in the conventional channel selecting apparatus, when the offset of the broadcast signal frequency to be received is larger than of the normal regular frequency, the number of times of correcting the frequency dividing ratio of the variable frequency divider adjusting the oscillated frequency of the VCO will increase and the tuning period must be increased to obtain a normal tuning.